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preliminary publication# 21606 rev: c amendment/ 0 issue date: april 1998 am29dl400b 4 megabit (512 k x 8-bit/256 k x 16-bit) cmos 3.0 volt-only, simultaneous operation flash memory distinctive characteristics n simultaneous read/write operations host system can program or erase in one bank, then immediately and simultaneously read from the other bank zero latency between read and write operations read-while-erase read-while-program n single power supply operation 2.7 to 3.6 volt read and write operations for battery-powered applications n manufactured on 0.35 m process technology n high performance access times as fast as 70 ns n low current consumption (typical values at 5 mhz) 7 ma active read current 21 ma active read-while-program or read-while- erase current 17 ma active program-while-erase-suspended current 200 na in standby mode 200 na in automatic sleep mode standard t ce chip enable access time applies to transition from automatic sleep mode to active mode n flexible sector architecture two 16 kword, two 8 kword, four 4 kword, and six 32 kword sectors in word mode two 32 kbyte, two 16 kbyte, four 8 kbyte, and six 64 kbyte sectors in byte mode any combination of sectors can be erased supports full chip erase n unlock bypass program command reduces overall programming time when issuing multiple program command sequences n sector protection hardware method of locking a sector to prevent any program or erase operation within that sector sectors can be locked in-system or via programming equipment temporary sector unprotect feature allows code changes in previously locked sectors n top or bottom boot block configurations available n embedded algorithms embedded erase algorithm automatically pre-programs and erases sectors or entire chip embedded program algorithm automatically programs and verifies data at specified address n minimum 1 million program/erase cycles guaranteed per sector n package options 44-pin so 48-pin tsop n compatible with jedec standards pinout and software compatible with single-power-supply flash standard superior inadvertent write protection n data# polling and toggle bits provides a software method of detecting program or erase cycle completion n ready/busy# output (ry/by#) hardware method for detecting program or erase cycle completion n erase suspend/erase resume suspends or resumes erasing sectors to allow reading and programming in other sectors no need to suspend if sector is in the other bank n hardware reset pin (reset#) hardware method of resetting the device to reading array data
2 am29dl400b preliminary general description the am29dl400b is an 4 mbit, 3.0 volt-only flash memory device, organized as 262,144 words or 524,288 bytes. the device is offered in 44-pin so and 48-pin tsop packages. the word-wide (x16) data ap- pears on dq0Cdq15; the byte-wide (x8) data appears on dq0Cdq7. this device requires only a single 3.0 volt v cc supply to perform read, program, and erase operations. a standard eprom programmer can also be used to program and erase the device. the standard device offers access times of 70, 80, 90, and 120 ns, allowing high-speed microprocessors to operate without wait states. standard control pins chip enable (ce#), write enable (we#), and output en- able (oe#)control read and write operations, and avoid bus contention issues. the device requires only a single 3.0 volt power sup- ply for both read and write functions. internally gener- ated and regulated voltages are provided for the program and erase operations. simultaneous read/write operations with zero latency the simultaneous read/write architecture provides si- multaneous operation by dividing the memory space into two banks. bank 1 contains boot/parameter sec- tors, and bank 2 consists of larger, code sectors of uni- form size. the device can improve overall system performance by allowing a host system to program or erase in one bank, then immediately and simultane- ously read from the other bank, with zero latency . this releases the system from waiting for the completion of program or erase operations. am29dl400b features the device offers complete compatibility with the jedec single-power-supply flash command set standard . commands are written to the command register using standard microprocessor write timings. register contents serve as input to an internal state machine that controls the erase and programming circuitry. write cycles also internally latch addresses and data needed for the programming and erase operations. reading data out of the device is similar to reading from other flash or eprom devices. device programming occurs by executing the program command sequence. this initiates the embedded program algorithman internal algorithm that auto- matically times the program pulse widths and verifies proper cell margin. the unlock bypass mode facili- tates faster programming times by requiring only two write cycles to program data instead of four. device erasure occurs by executing the erase com- mand sequence. this initiates the embedded erase algorithman internal algorithm that automatically preprograms the array (if it is not already programmed) before executing the erase operation. during erase, the device automatically times the erase pulse widths and verifies proper cell margin. the host system can detect whether a program or erase operation is complete by observing the ry/by# pin, or by reading the dq7 (data# polling) and dq6 (toggle) status bits . after a program or erase cycle has been completed, the device automatically returns to reading array data. the sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. the device is fully erased when shipped from the factory. hardware data protection measures include a low v cc detector that automatically inhibits write opera- tions during power transitions. the hardware sector protection feature disables both program and erase operations in any combination of the sectors of mem- ory. this can be achieved in-system or via program- ming equipment. the erase suspend feature enables the user to put erase on hold for any period of time to read data from, or program data to, any sector within that bank that is not selected for erasure. true background erase can thus be achieved. there is no need to suspend the erase operation if the read data is in the other bank. the hardware reset# pin terminates any operation in progress and resets the internal state machine to reading array data. the reset# pin may be tied to the system reset circuitry. a system reset would thus also reset the device to reading array data, enabling the sys- tem microprocessor to read the boot-up firmware from the flash memory. the device offers two power-saving features. when ad- dresses have been stable for a specified amount of time, the device enters the automatic sleep mode . the system can also place the device into the standby mode . power consumption is greatly reduced in both these modes. amds flash technology combines years of flash mem- ory manufacturing experience to produce the highest levels of quality, reliability, and cost effectiveness. the device electrically erases all bits within a sector simulta- neously via fowler-nordheim tunneling. the bytes are programmed one byte or word at a time using hot elec- tron injection.
am29dl400b 3 preliminary product selector guide note: see ac characteristics for full specifications. block diagram family part number am29dl400b speed options (full voltage range: v cc = 2.7 C 3.6 v) -70 -80 -90 -120 max access time (ns) 70 80 90 120 ce# access (ns) 70 80 90 120 oe# access (ns) 30 30 35 50 v cc v ss upper bank address a0Ca17 reset# we# ce# byte# dq0Cdq15 state control & command register ry/by# upper bank x-decoder y-decoder latches and control logic oe# byte# dq0Cdq15 lower bank y-decoder x-decoder latches and control logic lower bank address status control a0Ca17 a0Ca17 a0Ca17 a0Ca17 dq0Cdq15 dq0Cdq15 oe# byte# 21606c-1
4 am29dl400b preliminary connection diagrams 1 16 2 3 4 5 6 7 8 17 18 19 20 21 22 23 24 9 10 11 12 13 14 15 48 33 47 46 45 44 43 42 41 40 39 38 37 36 35 34 25 32 31 30 29 28 27 26 a15 nc a14 a13 a12 a11 a10 a9 a8 nc nc we# reset# nc nc ry/by# a1 a17 a7 a6 a5 a4 a3 a2 a16 dq2 byte# v ss dq15/a-1 dq7 dq14 dq6 dq13 dq9 dq1 dq8 dq0 oe# v ss ce# a0 dq5 dq12 dq4 v cc dq11 dq3 dq10 1 16 2 3 4 5 6 7 8 17 18 19 20 21 22 23 24 9 10 11 12 13 14 15 48 33 47 46 45 44 43 42 41 40 39 38 37 36 35 34 25 32 31 30 29 28 27 26 a15 nc a14 a13 a12 a11 a10 a9 a8 nc nc we# reset# nc nc ry/by# a1 a17 a7 a6 a5 a4 a3 a2 a16 dq2 byte# v ss dq15/a-1 dq7 dq14 dq6 dq13 dq9 dq1 dq8 dq0 oe# v ss ce# a0 dq5 dq12 dq4 v cc dq11 dq3 dq10 reverse tsop standard tsop 21606c-2
am29dl400b 5 preliminary connection diagrams 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 ry/by# nc a17 a7 a6 a5 a4 a3 a2 a1 a0 ce# v ss oe# dq0 dq8 dq1 dq9 dq2 dq10 dq3 dq11 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 reset# we# a8 a9 a10 a11 a12 a13 a14 a15 a16 byte# v ss dq15/a-1 dq7 dq14 dq6 dq13 dq5 dq12 dq4 v cc so 21606c-3
6 am29dl400b preliminary pin description a0-a17 = 18 addresses dq0-dq14 = 15 data inputs/outputs dq15/a-1 = dq15 (data input/output, word mode), a-1 (lsb address input, byte mode) ce# = chip enable oe# = output enable we# = write enable byte# = selects 8-bit or 16-bit mode reset# = hardware reset pin, active low ry/by# = ready/busy output v cc = 3.0 volt-only single power supply (see product selector guide for speed options and voltage supply tolerances) v ss = device ground nc = pin not connected internally logic symbol 21606c-4 18 16 or 8 dq0Cdq15 (a-1) a0Ca17 ce# oe# we# reset# byte# ry/by#
am29dl400b 7 preliminary ordering information standard products amd standard products are available in several packages and operating ranges. the order number (valid combination) is formed by a combination of the following: valid combinations valid combinations list configurations planned to be sup- ported in volume for this device. consult the local amd sales office to confirm availability of specific valid combinations to check on newly released combinations. device number/description am29dl400b 4 megabit (512 k x 8-bit/256 k x 16-bit) cmos flash memory 3.0 volt-only read, program, and erase am29dl400b -70 e c t optional processing blank = standard processing b = burn-in (contact an amd representative for more information) temperature range c= commercial (0c to +70c) i = industrial (C40c to +85c) e = extended (C55c to +125c) package type e = 40-pin thin small outline package (tsop) standard pinout (ts 040) f = 40-pin thin small outline package (tsop) reverse pinout (tsr040) s = 44-pin small outline package (so 044) speed option see product selector guide and valid combinations boot code sector architecture t = top sector b = bottom sector valid combinations am29dl400bt-70 am29dl400bb-70 ec, ei, fc, fi, sc, si am29dl400bt-80 am29dl400bb-80 ec, ei, ee, fc, fi, fe, sc, si, se am29dl400bt-90 am29dl400bb-90 am29dl400bt-120 am29dl400bb-120
8 am29dl400b preliminary device bus operations this section describes the requirements and use of the device bus operations, which are initiated through the internal command register. the command register it- self does not occupy any addressable memory loca- tion. the register is a latch used to store the commands, along with the address and data informa- tion needed to execute the command. the contents of the register serve as inputs to the internal state ma- chine. the state machine outputs dictate the function of the device. table 1 lists the device bus operations, the inputs and control levels they require, and the resulting output. the following subsections describe each of these operations in further detail. table 1. am29dl400b device bus operations legend: l = logic low = v il , h = logic high = v ih , v id = 12.0 0.5 v, x = dont care, a in = address in, d in = data in, d out = data out notes: 1. addresses are a17:a0 in word mode (byte# = v ih ), a17:a-1 in byte mode (byte# = v il ). 2. the sector protect and sector unprotect functions may also be implemented via programming equipment. see the sector protection/unprotection section. word/byte configuration the byte# pin controls whether the device data i/o pins operate in the byte or word configuration. if the byte# pin is set at logic 1, the device is in word con- figuration, dq0-15 are active and controlled by ce# and oe# . if the byte# pin is set at logic 0, the device is in byte configuration, and only data i/o pins dq0Cdq7 are ac- tive and controlled by ce# and oe#. the data i/o pins dq8Cdq14 are tri-stated, and the dq15 pin is used as an input for the lsb (a-1) address function. requirements for reading array data to read array data from the outputs, the system must drive the ce# and oe# pins to v il . ce# is the power control and selects the device. oe# is the output con- trol and gates array data to the output pins. we# should remain at v ih . the byte# pin determines whether the device outputs array data in words or bytes. the internal state machine is set for reading array data upon device power-up, or after a hardware reset. this ensures that no spurious alteration of the mem- ory content occurs during the power transition. no command is necessary in this mode to obtain array data. standard microprocessor read cycles that as- sert valid addresses on the device address inputs pro- duce valid data on the device data outputs. each bank remains enabled for read access until the command register contents are altered. see reading array data for more information. refer to the ac read-only operations table for timing spec- ifications and to figure 13 for the timing diagram. i cc1 in the dc characteristics table represents the active current specification for reading array data. writing commands/command sequences to write a command or command sequence (which in- cludes programming data to the device and erasing operation ce# oe# we# reset# addresses (note 1) dq0C dq7 dq8Cdq15 byte# = v ih byte# = v il read l l h h a in d out d out dq8Cdq14 = high-z, dq15 = a-1 write l h l h a in d in d in standby v cc 0.3 v xx v cc 0.3 v x high-z high-z high-z output disable l h h h x high-z high-z high-z reset x x x l x high-z high-z high-z sector protect (note 2) l h l v id sector address, a6 = l, a1 = h, a0 = l d in xx sector unprotect (note 2) l h l v id sector address, a6 = h, a1 = h, a0 = l d in xx temporary sector unprotect x x x v id a in d in d in high-z
am29dl400b 9 preliminary sectors of memory), the system must drive we# and ce# to v il , and oe# to v ih . for program operations, the byte# pin determines whether the device accepts program data in bytes or words. refer to word/byte configuration for more in- formation. the device features an unlock bypass mode to facili- tate faster programming. once a bank enters the unlock bypass mode, only two write cycles are required to pro- gram a word or byte, instead of four. the byte/word program command sequence section has details on programming data to the device using both standard and unlock bypass command sequences. an erase operation can erase one sector, multiple sec- tors, or the entire device. tables 2 and 3 indicate the address space that each sector occupies. the device address space is divided into two banks: bank 1 con- tains the boot/parameter sectors, and bank 2 contains the larger, code sectors of uniform size. a bank ad- dress is the address bits required to uniquely select a bank. similarly, a sector address is the address bits required to uniquely select a sector. if the system writes the autoselect command se- quence, the device enters the autoselect mode. the system can then read autoselect codes from the inter- nal register (which is separate from the memory array) on dq7Cdq0. standard read cycle timings apply in this mode. refer to the autoselect mode and autoselect command sequence sections for more information. i cc2 in the dc characteristics table represents the ac- tive current specification for the write mode. the ac characteristics section contains timing specification ta- bles and timing diagrams for write operations. simultaneous read/write operations with zero latency this device is capable of reading data from one bank of memory while programming or erasing in the other bank of memory. an erase operation may also be sus- pended to read from or program to another location within the same bank (except the sector being erased). figure 19 shows how read and write cycles may be in- itiated for simultaneous operation with zero latency. i cc6 and i cc7 in the dc characteristics table represent the current specifications for read-while-program and read-while-erase, respectively. standby mode when the system is not reading or writing to the device, it can place the device in the standby mode. in this mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state, inde- pendent of the oe# input. the device enters the cmos standby mode when the ce# and reset# pins are both held at v cc 0.3 v. (note that this is a more restricted voltage range than v ih .) if ce# and reset# are held at v ih , but not within v cc 0.3 v, the device will be in the standby mode, but the standby current will be greater. the device requires standard access time (t ce ) for read access when the device is in either of these standby modes, before it is ready to read data. the device also enters the standby mode when the re- set# pin is driven low. refer to the next section, re- set#: hardware reset pin. if the device is deselected during erasure or program- ming, the device draws active current until the operation is completed. i cc3 in the dc characteristics table represents the standby current specification. automatic sleep mode the automatic sleep mode minimizes flash device energy consumption. the device automatically enables this mode when addresses remain stable for t acc + 30 ns. the automatic sleep mode is independent of the ce#, we#, and oe# control signals. standard address access timings provide new data when addresses are changed. while in sleep mode, output data is latched and always available to the system. i cc4 in the dc characteristics table represents the automatic sleep mode current specification.
10 am29dl400b preliminary reset#: hardware reset pin the reset# pin provides a hardware method of reset- ting the device to reading array data. when the re- set# pin is driven low for at least a period of t rp , the device immediately terminates any operation in progress, tristates all output pins, and ignores all read/ write commands for the duration of the reset# pulse. the device also resets the internal state machine to reading array data. the operation that was interrupted should be reinitiated once the device is ready to accept another command sequence, to ensure data integrity. current is reduced for the duration of the reset# pulse. when reset# is held at v ss 0.3 v, the device draws cmos standby current (i cc4 ). if reset# is held at v il but not within v ss 0.3 v, the standby current will be greater. the reset# pin may be tied to the system reset cir- cuitry. a system reset would thus also reset the flash memory, enabling the system to read the boot-up firmware from the flash memory. if reset# is asserted during a program or erase oper- ation, the ry/by# pin remains a 0 (busy) until the in- ternal reset operation is complete, which requires a time of t ready (during embedded algorithms). the system can thus monitor ry/by# to determine whether the reset operation is complete. if reset# is asserted when a program or erase operation is not executing (ry/by# pin is 1), the reset operation is completed within a time of t ready (not during embedded algo- rithms). the system can read data t rh after the re- set# pin returns to v ih . refer to the ac characteristics tables for reset# pa- rameters and to figure 14 for the timing diagram. output disable mode when the oe# input is at v ih , output from the device is disabled. the output pins are placed in the high imped- ance state.
am29dl400b 11 preliminary table 2. am29dl400bt top boot sector architecture note: the address range is a17:a-1 if in byte mode (byte# = v il ). the address range is a17:a0 if in word mode (byte# = v ih ). bank sector sector address sector size (kbytes/ kwords) (x8) address range (x16) address range bank address a15 a14 a13 a12 a17 a16 bank 2 sa0 0 0 0 x x x 64/32 00000hC0ffffh 00000hC07fffh sa1 0 0 1 x x x 64/32 10000hC1ffffh 08000hC0ffffh sa2 0 1 0 x x x 64/32 20000hC2ffffh 10000hC17fffh sa3 0 1 1 x x x 64/32 30000hC3ffffh 18000hC1ffffh sa4 1 0 0 x x x 64/32 40000hC4ffffh 20000hC27fffh sa5 1 0 1 x x x 64/32 50000hC5ffffh 28000hC2ffffh bank 1 sa6 1 1 0 0 0 x 16/8 60000hC63fffh 30000hC31fffh sa7 1 1 0 01x 32/16 64000hC6bfffh 32000hC35fffh 10x sa8 1 1 0 1 1 0 8/4 6c000hC6dfffh 36000hC36fffh sa9 1 1 0 1 1 1 8/4 6e000hC6ffffh 37000hC37fffh sa10 1 1 1 0 0 0 8/4 70000hC71fffh 38000hC38fffh sa11 1 1 1 0 0 1 8/4 72000hC73fffh 39000hC39fffh sa12 1 1 1 01x 32/16 74000hC7bfffh 3a000hC3dfffh 10x sa13 1 1 1 1 1 x 16/8 7c000hC7ffffh 3e000hC3ffffh
12 am29dl400b preliminary table 3. am29dl400bb bottom boot sector architecture note: the address range is a17:a-1 if in byte mode (byte# = v il ). the address range is a17:a0 if in word mode (byte# = v ih ). autoselect mode the autoselect mode provides manufacturer and de- vice identification, and sector protection verification, through identifier codes output on dq7Cdq0. this mode is primarily intended for programming equipment to automatically match a device to be programmed with its corresponding programming algorithm. however, the autoselect codes can also be accessed in-system through the command register. when using programming equipment, the autoselect mode requires v id (11.5 v to 12.5 v) on address pin a9. address pins a6, a1, and a0 must be as shown in table 4. in addition, when verifying sector protection, the sector address must appear on the appropriate highest order address bits (see tables 2 and 3). table 4 shows the remaining address bits that are dont care. when all necessary bits have been set as required, the programming equipment may then read the corre- sponding identifier code on dq7-dq0. to access the autoselect codes in-system, the host system can issue the autoselect command via the command register, as shown in table 5. this method does not require v id . refer to the autoselect command sequence section for more information. bank sector sector address sector size (kbytes/kwords) (x8) address range (x16) address range bank address a15 a14 a13 a12 a17 a16 bank 2 sa13 1 1 1 x x x 64/32 70000hC7ffffh 38000hC3ffffh sa12 1 1 0 x x x 64/32 60000hC6ffffh 30000hC37fffh sa11 1 0 1 x x x 64/32 50000hC5ffffh 28000hC2ffffh sa10 1 0 0 x x x 64/32 40000hC4ffffh 20000hC27fffh sa9 0 1 1 x x x 64/32 30000hC3ffffh 18000hC1ffffh sa8 0 1 0 x x x 64/32 20000hC2ffffh 10000hC17fffh bank 1 sa7 0 0 1 1 1 x 16/8 1c000hC1ffffh 0e000hC0ffffh sa6 0 0 1 10x 32/16 14000hC1bfffh 0a000hC0dfffh 01x sa5 0 0 1 0 0 1 8/4 12000hC13fffh 09000hC09fffh sa4 0 0 1 0 0 0 8/4 10000hC11fffh 08000hC08fffh sa3 0 0 0 1 1 1 8/4 0e000hC0ffffh 07000hC07fffh sa2 0 0 0 1 1 0 8/4 0c000hC0dfffh 06000hC06fffh sa1 0 0 0 10x 32/16 04000hC0bfffh 02000hC05fffh 01x sa0 0 0 0 0 0 x 16/8 00000hC03fffh 00000hC01fffh
am29dl400b 13 preliminary table 4. am29dl400b autoselect codes (high voltage method) note: l = logic low = v il , h = logic high = v ih , ba = bank address, sa = sector address, x = dont care. sector protection/unprotection the hardware sector protection feature disables both program and erase operations in any sector. the hard- ware sector unprotection feature re-enables both pro- gram and erase operations in previously protected sectors. sector protection/unprotection can be imple- mented via two methods. the primary method requires v id on the reset# pin only, and can be implemented either in-system or via programming equipment. figure 2 shows the algo- rithms and figure 24 shows the timing diagram. this method uses standard microprocessor bus cycle tim- ing. for sector unprotect, all unprotected sectors must first be protected prior to the first sector unprotect write cycle. the alternate method intended only for programming equipment requires v id on address pin a9 and oe#. this method is compatible with programmer routines written for earlier 3.0 volt-only amd flash devices. pub- lication number 22145 contains further details; contact an amd representative to request a copy. the device is shipped with all sectors unprotected. amd offers the option of programming and protecting sectors at its factory prior to shipping the device through amds expressflash? service. contact an amd representative for details. it is possible to determine whether a sector is protected or unprotected. see the autoselect mode section for details. temporary sector unprotect this feature allows temporary unprotection of previ- ously protected sectors to change data in-system. the sector unprotect mode is activated by setting the re- set# pin to v id (11.5 v C 12.5 v). during this mode, formerly protected sectors can be programmed or erased by selecting the sector addresses. once v id is removed from the reset# pin, all the previously pro- tected sectors are protected again. figure 1 shows the algorithm, and figure 23 shows the timing diagrams, for this feature. figure 1. temporary sector unprotect operation description mode ce# oe# we# a17 to a12 a11 to a10 a9 a8 to a7 a6 a5 to a2 a1 a0 dq8 to dq15 dq7 to dq0 manufacturer id : amd l l h ba x v id xlxll x 01h device id: am29dl400b (top boot block) word l l h ba x v id xlxlh 22h 0c byte l l h x 0c device id: am29dl400b (bottom boot block) word l l h ba x v id xlxlh 22h 0f byte l l h x 0f sector protection verification l l h sa x v id xlxhl x 01h (protected) x 00h (unprotected) start perform erase or program operations reset# = v ih temporary sector unprotect completed (note 2) reset# = v id (note 1) notes: 1. all protected sectors unprotected. 2. all previously protected sectors are protected once again. 21606c-5
14 am29dl400b preliminary figure 2. in-system sector protect/unprotect algorithms sector protect: write 60h to sector address with a6 = 0, a1 = 1, a0 = 0 set up sector address wait 150 s verify sector protect: write 40h to sector address with a6 = 0, a1 = 1, a0 = 0 read from sector address with a6 = 0, a1 = 1, a0 = 0 start plscnt = 1 reset# = v id wait 1 m s first write cycle = 60h? data = 01h? remove v id from reset# write reset command sector protect complete yes yes no plscnt = 25? yes device failed increment plscnt temporary sector unprotect mode no sector unprotect: write 60h to sector address with a6 = 1, a1 = 1, a0 = 0 set up first sector address wait 15 ms verify sector unprotect: write 40h to sector address with a6 = 1, a1 = 1, a0 = 0 read from sector address with a6 = 1, a1 = 1, a0 = 0 start plscnt = 1 reset# = v id wait 1 m s data = 00h? last sector verified? remove v id from reset# write reset command sector unprotect complete yes no plscnt = 1000? yes device failed increment plscnt temporary sector unprotect mode no all sectors protected? yes protect all sectors: the indicated portion of the sector protect algorithm must be performed for all unprotected sectors prior to issuing the first sector unprotect address set up next sector address no yes no yes no no yes no sector protect algorithm sector unprotect algorithm first write cycle = 60h? protect another sector? reset plscnt = 1 21606c-6
am29dl400b 15 preliminary hardware data protection the command sequence requirement of unlock cycles for programming or erasing provides data protection against inadvertent writes (refer to table 5 for com- mand definitions). in addition, the following hardware data protection measures prevent accidental erasure or programming, which might otherwise be caused by spurious system level signals during v cc power-up and power-down transitions, or from system noise. low v cc write inhibit when v cc is less than v lko , the device does not accept any write cycles. this protects data during v cc power-up and power-down. the command register and all internal program/erase circuits are disabled, and the device resets to reading array data. subsequent writes are ignored until v cc is greater than v lko . the system must provide the proper signals to the control pins to prevent unintentional writes when v cc is greater than v lko . write pulse glitch protection noise pulses of less than 5 ns (typical) on oe#, ce# or we# do not initiate a write cycle. logical inhibit write cycles are inhibited by holding any one of oe# = v il , ce# = v ih or we# = v ih . to initiate a write cycle, ce# and we# must be a logical zero while oe# is a logical one. power-up write inhibit if we# = ce# = v il and oe# = v ih during power up, the device does not accept commands on the rising edge of we#. the internal state machine is automatically reset to reading array data on power-up. command definitions writing specific address and data commands or se- quences into the command register initiates device op- erations. table 5 defines the valid register command sequences. writing incorrect address and data val- ues or writing them in the improper sequence resets the device to reading array data. all addresses are latched on the falling edge of we# or ce#, whichever happens later. all data is latched on the rising edge of we# or ce#, whichever happens first. refer to the appropriate timing diagrams in the ac characteristics section. reading array data the device is automatically set to reading array data after device power-up. no commands are required to retrieve data. each bank is ready to read array data after completing an embedded program or embedded erase algorithm. after the device accepts an erase suspend command, the corresponding bank enters the erase-suspend- read mode, after which the system can read data from any non-erase-suspended sector within the same bank. after completing a programming operation in the erase suspend mode, the system may once again read array data with the same exception. see the erase suspend/erase resume commands section for more information. the system must issue the reset command to return a bank to the read (or erase-suspend-read) mode if dq5 goes high during an active program or erase operation, or if the bank is in the autoselect mode. see the next section, reset command, for more information. see also requirements for reading array data in the device bus operations section for more information. the read-only operations table provides the read pa- rameters, and figure 13 shows the timing diagram. reset command writing the reset command resets the banks to the read or erase-suspend-read mode. address bits are dont cares for this command. the reset command may be written between the se- quence cycles in an erase command sequence before erasing begins. this resets the bank to which the sys- tem was writing to reading array data. once erasure begins, however, the device ignores reset commands until the operation is complete. the reset command may be written between the se- quence cycles in a program command sequence be- fore programming begins. this resets the bank to which the system was writing to the reading array data. if the program command sequence is written to a bank that is in the erase suspend mode, writing the reset command returns that bank to the erase-suspend-read mode. once programming begins, however, the device ignores reset commands until the operation is com- plete. the reset command may be written between the se- quence cycles in an autoselect command sequence. once in the autoselect mode, the reset command must be written to return to reading array data. if a bank en- tered the autoselect mode while in the erase suspend mode, writing the reset command returns that bank to the erase-suspend-read mode. if dq5 goes high during a program or erase operation, writing the reset command returns the banks to reading array data (or erase-suspend-read mode if that bank was in erase suspend).
16 am29dl400b preliminary autoselect command sequence the autoselect command sequence allows the host system to access the manufacturer and devices codes, and determine whether or not a sector is protected. table 5 shows the address and data requirements. this method is an alternative to that shown in table 4, which is intended for prom programmers and requires v id on address pin a9. the autoselect command sequence may be written to an address within a bank that is either in the read or erase-suspend-read mode. the autose- lect command may not be written while the device is actively programming or erasing in the other bank. the autoselect command sequence is initiated by first writing two unlock cycles. this is followed by a third write cycle that contains the bank address and the au- toselect command. the addressed bank then enters the autoselect mode. the system may read at any ad- dress within the same bank any number of times with- out initiating another autoselect command sequence: n a read cycle at address (ba)xx00h (where ba is the bank address) returns the manufacturer code. n a read cycle at address (ba)xx01h in word mode (or (ba)xx02h in byte mode) returns the device code. n a read cycle to an address containing a sector ad- dress (sa) within the same bank, and the address 02h on a7Ca0 in word mode (or the address 04h on a6Ca-1 in byte mode) returns 01h if the sector is protected, or 00h if it is unprotected. refer to tables 2 and 3 for valid sector addresses. the system may continue to read array data from the other bank while a bank is in the autoselect mode. to exit the autoselect mode, the system must write the reset command to return both banks to reading array data. if a bank enters the autoselect mode while erase suspended, a reset command returns that bank to the erase-suspend-read mode. a subsequent erase resume command returns the bank to the erase oper- ation. byte/word program command sequence the system may program the device by word or byte, depending on the state of the byte# pin. program- ming is a four-bus-cycle operation. the program com- mand sequence is initiated by writing two unlock write cycles, followed by the program set-up command. the program address and data are written next, which in turn initiate the embedded program algorithm. the system is not required to provide further controls or tim- ings. the device automatically generates the program pulses and verifies the programmed cell margin. table 5 shows the address and data requirements for the byte program command sequence. when the embedded program algorithm is complete, that bank then returns to reading array data and ad- dresses are no longer latched. the system can deter- mine the status of the program operation by using dq7, dq6, or ry/by#. note that while the embedded pro- gram operation is in progress, the system can read data from the non-programming bank. refer to the write operation status section for information on these status bits. any commands written to the device during the em- bedded program algorithm are ignored. note that a hardware reset immediately terminates the program operation. the program command sequence should be reinitiated once that bank has returned to reading array data, to ensure data integrity. programming is allowed in any sequence and across sector boundaries. a bit cannot be programmed from 0 back to a 1. attempting to do so may cause that bank to set dq5 = 1, or cause the dq7 and dq6 status bits to indicate the operation was successful. however, a succeeding read will show that the data is still 0. only erase operations can convert a 0 to a 1. unlock bypass command sequence the unlock bypass feature allows the system to pro- gram bytes or words to a bank faster than using the standard program command sequence. the unlock by- pass command sequence is initiated by first writing two unlock cycles. this is followed by a third write cycle containing the unlock bypass command, 20h. that bank then enters the unlock bypass mode. a two-cycle unlock bypass program command sequence is all that is required to program in this mode. the first cycle in this sequence contains the unlock bypass program command, a0h; the second cycle contains the program address and data. additional data is programmed in the same manner. this mode dispenses with the initial two unlock cycles required in the standard program command sequence, resulting in faster total program- ming time. table 5 shows the requirements for the com- mand sequence. during the unlock bypass mode, only the unlock bypass program and unlock bypass reset commands are valid. to exit the unlock bypass mode, the system must issue the two-cycle unlock bypass reset command se- quence. the first cycle must contain the bank address and the data 90h. the second cycle need only contain the data 00h. the bank then returns to reading array data.
am29dl400b 17 preliminary figure 3 illustrates the algorithm for the program oper- ation. refer to the erase and program operations table in the ac characteristics section for parameters, and figure 17 for timing diagrams. note: see table 5 for program command sequence. figure 3. program operation chip erase command sequence chip erase is a six bus cycle operation. the chip erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. two additional unlock write cycles are then followed by the chip erase command, which in turn invokes the embedded erase algorithm. the device does not require the system to preprogram prior to erase. the embedded erase algo- rithm automatically preprograms and verifies the entire memory for an all zero data pattern prior to electrical erase. the system is not required to provide any con- trols or timings during these operations. table 5 shows the address and data requirements for the chip erase command sequence. when the embedded erase algorithm is complete, that bank returns to reading array data and addresses are no longer latched. the system can determine the sta- tus of the erase operation by using dq7, dq6, dq2, or ry/by#. refer to the write operation status section for information on these status bits. any commands written during the chip erase operation are ignored. however, note that a hardware reset im- mediately terminates the erase operation. if that oc- curs, the chip erase command sequence should be reinitiated once that bank has returned to reading array data, to ensure data integrity. figure 4 illustrates the algorithm for the erase opera- tion. refer to the erase and program operations tables in the ac characteristics section for parameters, and figure 18 section for timing diagrams. sector erase command sequence sector erase is a six bus cycle operation. the sector erase command sequence is initiated by writing two un- lock cycles, followed by a set-up command. two addi- tional unlock cycles are written, and are then followed by the address of the sector to be erased, and the sec- tor erase command. table 5 shows the address and data requirements for the sector erase command se- quence. the device does not require the system to preprogram prior to erase. the embedded erase algorithm auto- matically programs and verifies the entire memory for an all zero data pattern prior to electrical erase. the system is not required to provide any controls or tim- ings during these operations. after the command sequence is written, a sector erase time-out of 50 s occurs. during the time-out period, additional sector addresses and sector erase com- mands may be written. loading the sector erase buffer may be done in any sequence, and the number of sec- tors may be from one sector to all sectors. the time be- tween these additional cycles must be less than 50 s, otherwise the last address and command may not be accepted, and erasure may begin. it is recommended that processor interrupts be disabled during this time to ensure all commands are accepted. the interrupts can be re-enabled after the last sector erase command is written. any command other than sector erase or erase suspend during the time-out period resets that bank to reading array data. the system must re- write the command sequence and any additional ad- dresses and commands. the system can monitor dq3 (in the erasing bank) to determine if the sector erase timer has timed out (see the section on dq3: sector erase timer.). the time-out begins from the rising edge of the final we# pulse in the command sequence. when the embedded erase algorithm is complete, the bank returns to reading array data and addresses are no longer latched. note that while the embedded erase operation is in progress, the system can read data from start write program command sequence data poll from system verify data? no yes last address? no yes programming completed increment address embedded program algorithm in progress 21606c-7
18 am29dl400b preliminary the non-erasing bank. the system can determine the status of the erase operation by reading dq7, dq6, dq2, or ry/by# in the erasing bank. refer to the write operation status section for information on these sta- tus bits. once the sector erase operation has begun, only the erase suspend command is valid. all other commands are ignored. however, note that a hardware reset im- mediately terminates the erase operation. if that oc- curs, the sector erase command sequence should be reinitiated once that bank has returned to reading array data, to ensure data integrity. figure 4 illustrates the algorithm for the erase opera- tion. refer to the erase and program operations tables in the ac characteristics section for parameters, and figure 18 section for timing diagrams. erase suspend/erase resume commands the erase suspend command, b0h, allows the sys- tem to interrupt a sector erase operation and then read data from, or program data to, any sector not se- lected for erasure. the bank address is required when writing this command. this command is valid only dur- ing the sector erase operation, including the 50 s time-out period during the sector erase command se- quence. the erase suspend command is ignored if written during the chip erase operation or embedded program algorithm. when the erase suspend command is written during the sector erase operation, the device requires a max- imum of 20 s to suspend the erase operation. how- ever, when the erase suspend command is written during the sector erase time-out, the device immedi- ately terminates the time-out period and suspends the erase operation. after the erase operation has been suspended, the bank enters the erase-suspend-read mode. the sys- tem can read data from or program data to any sector not selected for erasure. (the device erase suspends all sectors selected for erasure.) reading at any ad- dress within erase-suspended sectors produces status information on dq7Cdq0. the system can use dq7, or dq6 and dq2 together, to determine if a sector is actively erasing or is erase-suspended. refer to the write operation status section for information on these status bits. after an erase-suspended program operation is com- plete, the bank returns to the erase-suspend-read mode. the system can determine the status of the pro- gram operation using the dq7 or dq6 status bits, just as in the standard byte program operation. refer to the write operation status section for more information. in the erase-suspend-read mode, the system can also issue the autoselect command sequence. refer to the autoselect mode and autoselect command sequence sections for details. to resume the sector erase operation, the system must write the erase resume command. the bank address of the erase-suspended bank is required when writing this command. further writes of the resume command are ignored. another erase suspend command can be written after the chip has resumed erasing. notes: 1. see table 5 for erase command sequence. 2. see the section on dq3 for information on the sector erase timer. figure 4. erase operation start write erase command sequence (notes 1, 2) data poll to erasing bank from system data = ffh? no yes erasure completed embedded erase algorithm in progress 21606c-8
am29dl400b 19 preliminary table 5. am29dl400b command definitions legend: x = dont care ra = address of the memory location to be read. rd = data read from location ra during read operation. pa = address of the memory location to be programmed. addresses latch on the falling edge of the we# or ce# pulse, whichever happens later. pd = data to be programmed at location pa. data latches on the rising edge of we# or ce# pulse, whichever happens first. sa = address of the sector to be verified (in autoselect mode) or erased. address bits a17Ca12 uniquely select any sector. ba = address of the bank that is being switched to autoselect mode, is in bypass mode, or is being erased. address bits a17C a16 select a bank. notes: 1. see table 1 for description of bus operations. 2. all values are in hexadecimal. 3. except when reading array or autoselect data, all bus cycles are write operations. 4. data bits dq15Cdq8 are dont cares for unlock and command cycles in word mode. 5. address bits a17Ca11 are dont cares for unlock and command cycles, unless bank address (ba) is required. 6. no unlock or command cycles required when bank is in read mode. 7. the reset command is required to return to reading array data (or to the erase-suspend-read mode if previously in erase suspend) when a bank is in the autoselect mode, or if dq5 is goes high (while the bank is providing status information). 8. the fourth cycle of the autoselect command sequence is a read cycle. the system must provide the bank address to obtain the manufacturer or device id information. 9. the data is 00h for an unprotected sector and 01h for a protected sector. see the autoselect command sequence section for more information. 10. the unlock bypass command is required prior to the unlock bypass program command. 11. the unlock bypass reset command is required to return to reading array data when the bank is in the unlock bypass mode. 12. the system may read and program in non-erasing sectors, or enter the autoselect mode, when in the erase suspend mode. the erase suspend command is valid only during a sector erase operation, and requires the bank address. 13. the erase resume command is valid only during the erase suspend mode, and requires the bank address. command sequence (note 1) bus cycles (notes 2C5) first second third fourth fifth sixth addr data addr data addr data addr data addr data addr data read (note 6) 1 ra rd reset (note 7) 1 xxx f0 manufacturer id word 4 555 aa 2aa 55 (ba)555 90 (ba)x00 01 byte aaa 555 (ba)aaa device id, top boot block word 4 555 aa 2aa 55 (ba)555 90 (ba)x01 220c byte aaa 555 (ba)aaa (ba)x02 0c device id, bottom boot block word 4 555 aa 2aa 55 (ba)555 90 (ba)x01 220f byte aaa 555 (ba)aaa (ba)x02 0f sector protect verify (note 9) word 4 555 aa 2aa 55 (ba)555 90 (sa) x02 xx00 xx01 byte aaa 555 (ba)aaa (sa) x04 00 01 program word 4 555 aa 2aa 55 555 a0 pa pd byte aaa 555 aaa unlock bypass word 3 555 aa 2aa 55 555 20 byte aaa 555 aaa unlock bypass program (note 10) 2 xxx a0 pa pd unlock bypass reset (note 11) 2 ba 90 xxx 00 chip erase word 6 555 aa 2aa 55 555 80 555 aa 2aa 55 555 10 byte aaa 555 aaa aaa 555 aaa sector erase word 6 555 aa 2aa 55 555 80 555 aa 2aa 55 sa 30 byte aaa 555 aaa aaa 555 erase suspend (note 12) 1 ba b0 erase resume (note 13) 1 ba 30 cycles autoselect (note 8)
20 am29dl400b preliminary write operation status the device provides several bits to determine the sta- tus of a write operation in the bank where a program or erase operation is in progress: dq2, dq3, dq5, dq6, dq7, and ry/by#. table 6 and the following subsec- tions describe the function of these bits. dq7, ry/by#, and dq6 each offer a method for determining whether a program or erase operation is complete or in progress. these three bits are discussed first. dq7: data# polling the data# polling bit, dq7, indicates to the host sys- tem whether an embedded program or erase algo- rithm is in progress or completed, or whether a bank is in erase suspend. data# polling is valid after the rising edge of the final we# pulse in the command sequence. during the embedded program algorithm, the device outputs on dq7 the complement of the datum pro- grammed to dq7. this dq7 status also applies to pro- gramming during erase suspend. when the embedded program algorithm is complete, the device outputs the datum programmed to dq7. the system must provide the program address to read valid status information on dq7. if a program address falls within a protected sector, data# polling on dq7 is active for ap- proximately 1 s, then that bank returns to reading array data. during the embedded erase algorithm, data# polling produces a 0 on dq7. when the embedded erase al- gorithm is complete, or if the bank enters the erase suspend mode, data# polling produces a 1 on dq7. the system must provide an address within any of the sectors selected for erasure to read valid status infor- mation on dq7. after an erase command sequence is written, if all sec- tors selected for erasing are protected, data# polling on dq7 is active for approximately 100 s, then the bank returns to reading array data. if not all selected sectors are protected, the embedded erase algorithm erases the unprotected sectors, and ignores the se- lected sectors that are protected. however, if the sys- tem reads dq7 at an address within a protected sector, the status may not be valid. just prior to the completion of an embedded program or erase operation, dq7 may change asynchronously with dq0Cdq6 while output enable (oe#) is asserted low. that is, the device may change from providing sta- tus information to valid data on dq7. depending on when the system samples the dq7 output, it may read the status or valid data. even if the device has com- pleted the program or erase operation and dq7 has valid data, the data outputs on dq0Cdq6 may be still invalid. valid data on dq0Cdq7 will appear on succes- sive read cycles. table 6 shows the outputs for data# polling on dq7. figure 5 shows the data# polling algorithm. figure 20 in the ac characteristics section shows the data# poll- ing timing diagram. notes: 1. va = valid address for programming. during a sector erase operation, a valid address is any sector address within the sector being erased. during chip erase, a valid address is any non-protected sector address. 2. dq7 should be rechecked even if dq5 = 1 because dq7 may change simultaneously with dq5. figure 5. data# polling algorithm dq7 = data? yes no no dq5 = 1? no yes yes fail pass read dq7Cdq0 addr = va read dq7Cdq0 addr = va dq7 = data? start 21606c-9
am29dl400b 21 preliminary ry/by#: ready/busy# the ry/by# is a dedicated, open-drain output pin that indicates whether an embedded algorithm is in progress or complete. the ry/by# status is valid after the rising edge of the final we# pulse in the command sequence. since ry/by# is an open-drain output, sev- eral ry/by# pins can be tied together in parallel with a pull-up resistor to v cc . if the output is low (busy), the device is actively erasing or programming. (this includes programming in the erase suspend mode.) if the output is high (ready), the device is ready to read array data, is in the standby mode, or one of the banks is in the erase-suspend-read mode. table 6 shows the outputs for ry/by#. dq6: toggle bit i toggle bit i on dq6 indicates whether an embedded program or erase algorithm is in progress or complete, or whether the device has entered the erase suspend mode. toggle bit i may be read at any address within the programming or erasing bank, and is valid after the rising edge of the final we# pulse in the command se- quence (prior to the program or erase operation), and during the sector erase time-out. during an embedded program or erase algorithm op- eration, successive read cycles to any address within the programming or erasing bank cause dq6 to toggle. the system may use either oe# or ce# to control the read cycles. when the operation is complete, dq6 stops toggling. after an erase command sequence is written, if all sec- tors selected for erasing are protected, dq6 toggles for approximately 100 s, then returns to reading array data. if not all selected sectors are protected, the em- bedded erase algorithm erases the unprotected sec- tors, and ignores the selected sectors that are protected. the system can use dq6 and dq2 together to deter- mine whether a sector is actively erasing or is erase- suspended. when a bank is actively erasing (that is, the embedded erase algorithm is in progress), dq6 toggles. when that bank enters the erase suspend mode, dq6 stops toggling. however, the system must also use dq2 to determine which sectors are erasing or erase-suspended. alternatively, the system can use dq7 (see the subsection on dq7: data# polling). if a program address falls within a protected sector, dq6 toggles for approximately 1 s after the program command sequence is written, then returns to reading array data. dq6 also toggles during the erase-suspend-program mode, and stops toggling once the embedded pro- gram algorithm is complete. table 6 shows the outputs for toggle bit i on dq6. fig- ure 6 shows the toggle bit algorithm. figure 21 in the ac characteristics section shows the toggle bit timing diagrams. figure 22 shows the differences between dq2 and dq6 in graphical form. see also the subsec- tion on dq2: toggle bit ii. dq2: toggle bit ii the toggle bit ii on dq2, when used with dq6, indi- cates whether a particular sector is actively erasing (that is, the embedded erase algorithm is in progress), or whether that sector is erase-suspended. toggle bit ii is valid after the rising edge of the final we# pulse in the command sequence. dq2 toggles when the system reads at addresses within those sectors that have been selected for eras- ure. (the system may use either oe# or ce# to control the read cycles.) but dq2 cannot distinguish whether the sector is actively erasing or is erase-suspended. dq6, by comparison, indicates whether the device is actively erasing, or is in erase suspend, but cannot dis- tinguish which sectors are selected for erasure. thus, both status bits are required for sector and mode infor- mation. refer to table 6 to compare outputs for dq2 and dq6. figure 6 shows the toggle bit algorithm in flowchart form, and the section dq2: toggle bit ii explains the algorithm. see also the dq6: toggle bit i subsection. figure 21 shows the toggle bit timing diagram. figure 22 shows the differences between dq2 and dq6 in graphical form. reading toggle bits dq6/dq2 refer to figure 6 for the following discussion. whenever the system initially begins reading toggle bit status, it must read dq7Cdq0 at least twice in a row to determine whether a toggle bit is toggling. typically, the system would note and store the value of the toggle bit after the first read. after the second read, the system would com- pare the new value of the toggle bit with the first. if the toggle bit is not toggling, the device has completed the program or erase operation. the system can read array data on dq7Cdq0 on the following read cycle. however, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the sys- tem also should note whether the value of dq5 is high (see the section on dq5). if it is, the system should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as dq5 went high. if the toggle bit is no longer toggling, the device has successfully completed the program or erase operation. if it is still toggling, the device did not
22 am29dl400b preliminary completed the operation successfully, and the system must write the reset command to return to reading array data. the remaining scenario is that the system initially de- termines that the toggle bit is toggling and dq5 has not gone high. the system may continue to monitor the toggle bit and dq5 through successive read cycles, de- termining the status as described in the previous para- graph. alternatively, it may choose to perform other system tasks. in this case, the system must start at the beginning of the algorithm when it returns to determine the status of the operation (top of figure 6). note: the system should recheck the toggle bit even if dq5 = 1 because the toggle bit may stop toggling as dq5 changes to 1. see the subsections on dq6 and dq2 for more information. figure 6. toggle bit algorithm dq5: exceeded timing limits dq5 indicates whether the program or erase time has exceeded a specified internal pulse count limit. under these conditions dq5 produces a 1, indicating that the program or erase cycle was not successfully com- pleted. the device may output a 1 on dq5 if the system tries to program a 1 to a location that was previously pro- grammed to 0. only an erase operation can change a 0 back to a 1. under this condition, the device halts the operation, and when the timing limit has been exceeded, dq5 produces a 1. under both these conditions, the system must write the reset command to return to reading array data (or to the erase-suspend-read mode if a bank was previously in the erase-suspend-program mode). dq3: sector erase timer after writing a sector erase command sequence, the system may read dq3 to determine whether or not erasure has begun. (the sector erase timer does not apply to the chip erase command.) if additional sectors are selected for erasure, the entire time-out also ap- plies after each additional sector erase command. when the time-out period is complete, dq3 switches from a 0 to a 1. if the system can guarantee the time between additional sector erase commands to be less than 50 s, it need not monitor dq3. see also the sec- tor erase command sequence section. after the sector erase command is written, the system should read the status of dq7 (data# polling) or dq6 (toggle bit i) to ensure that the device has accepted the command sequence, and then read dq3. if dq3 is 1, the embedded erase algorithm has begun; all fur- ther commands (except erase suspend) are ignored until the erase operation is complete. if dq3 is 0, the device will accept additional sector erase commands. to ensure the command has been accepted, the sys- tem software should check the status of dq3 prior to and following each subsequent sector erase command. if dq3 is high on the second status check, the last com- mand might not have been accepted. table 6 shows the status of dq3 relative to the other status bits. start no yes yes dq5 = 1? no yes toggle bit = toggle? no program/erase operation not complete, write reset command program/erase operation complete read dq7Cdq0 toggle bit = toggle? read dq7Cdq0 twice read dq7Cdq0
am29dl400b 23 preliminary table 6. write operation status notes: 1. dq5 switches to 1 when an embedded program or embedded erase operation has exceeded the maximum timing limits. refer to the section on dq5 for more information. 2. dq7 and dq2 require a valid address when reading status information. refer to the appropriate subsection for further details. 3. when reading write operation status bits, the system must always provide the bank address where the embedded algorithm is in progress. the device outputs array data if the system addresses a non-busy bank. status dq7 (note 2) dq6 dq5 (note 1) dq3 dq2 (note 2) ry/by# standard mode embedded program algorithm dq7# toggle 0 n/a no toggle 0 embedded erase algorithm 0 toggle 0 1 toggle 0 erase suspend mode erase-suspend- read erase suspended sector 1 no toggle 0 n/a toggle 1 non-erase suspended sector data data data data data 1 erase-suspend-program dq7# toggle 0 n/a n/a 0
24 am29dl400b preliminary absolute maximum ratings storage temperature plastic packages . . . . . . . . . . . . . . . C65 c to +150 c ambient temperature with power applied. . . . . . . . . . . . . . C65 c to +125 c voltage with respect to ground v cc (note 1) . . . . . . . . . . . . . . . . . C0.5 v to +4.0 v a9 , oe# , and reset# (note 2). . . . . . . . .C0.5 v to +12.5 v all other pins (note 1) . . . . . . . . . . . . . . . . . C0.5 v to v cc +0.5 v output short circuit current (note 3) . . . . . . 200 ma notes: 1. minimum dc voltage on input or i/o pins is C0.5 v. during voltage transitions, input or i/o pins may undershoot v ss to C2.0 v for periods of up to 20 ns. maximum dc voltage on input or i/o pins is v cc +0.5 v. see figure 7. during voltage transitions, input or i/o pins may overshoot to v cc +2.0 v for periods up to 20 ns. see figure 8. 2. minimum dc input voltage on pins a9, oe#, and reset# is C0.5 v. during voltage transitions, a9, oe#, and reset# may undershoot v ss to C2.0 v for periods of up to 20 ns. see figure 7. maximum dc input voltage on pin a9 is +12.5 v which may overshoot to 14.0 v for periods up to 20 ns. 3. no more than one output may be shorted to ground at a time. duration of the short circuit should not be greater than one second. stresses above those listed under absolute maximum rat- ings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the opera- tional sections of this data sheet is not implied. exposure of the device to absolute maximum rating conditions for ex- tended periods may affect device reliability. figure 7. maximum negative overshoot waveform figure 8. maximum positive overshoot waveform operating ranges commercial (c) devices ambient temperature (t a ) . . . . . . . . . . . 0c to +70c industrial (i) devices ambient temperature (t a ) . . . . . . . . . C40c to +85c extended (e) devices ambient temperature (t a ) . . . . . . . . C55c to +125c v cc supply voltages v cc for all devices . . . . . . . . . . . . . . . . . 2.7 v to 3.6 v operating ranges define those limits between which the func- tionality of the device is guaranteed. 20 ns 20 ns +0.8 v C0.5 v 20 ns C2.0 v 21606c-11 20 ns 20 ns v cc +2.0 v v cc +0.5 v 20 ns 2.0 v 21606c-12
am29dl400b 25 preliminary dc characteristics cmos compatible notes: 1. the i cc current listed is typically less than 2 ma/mhz, with oe# at v ih . 2. i cc active while embedded erase or embedded program is in progress. 3. automatic sleep mode enables the low power mode when addresses remain stable for t acc + 30 ns. typical sleep mode current is 200 na. 4. not 100% tested. parameter symbol parameter description test conditions min typ max unit i li input load current v in = v ss to v cc , v cc = v cc max 1.0 a i lit a9 input load current v cc = v cc max ; a9 = 12.5 v 35 a i lo output leakage current v out = v ss to v cc , v cc = v cc max 1.0 a i cc1 v cc active read current (note 1) ce# = v il, oe# = v ih , byte mode 5 mhz 7 12 ma 1 mhz 2 4 ce# = v il, oe# = v ih , word mode 5 mhz 7 12 1 mhz 2 4 i cc2 v cc active write current (note 2) ce# = v il, oe# = v ih , we# = v il 15 30 ma i cc3 v cc standby current (ce# controlled) v cc = v cc max ; oe# = v il ; ce#, reset# = v cc 0.3 v 0.2 5 a i cc4 v cc reset current (reset# controlled) v cc = v cc max ; reset# = v ss 0.3 v 0.2 5 a i cc5 automatic sleep mode (note 3) v ih = v cc 0.3 v; v il = v ss 0.3 v 0.2 5 a i cc6 v cc active read-while- program current (notes 1, 4) ce# = v il, oe# = v ih byte 21 45 ma word 21 45 i cc7 v cc active read-while-erase current (notes 1, 4) ce# = v il, oe# = v ih byte 21 45 ma word 21 45 i cc8 v cc active program-while- erase-suspended current (note 4) ce# = v il, oe# = v ih 17 35 ma v il input low voltage C0.5 0.8 v v ih input high voltage 0.7 x v cc v cc + 0.3 v v id voltage for autoselect and temporary sector unprotect v cc = 3.0 v 10% 11.5 12.5 v v ol output low voltage i ol = 4.0 ma, v cc = v cc min 0.45 v v oh1 output high voltage i oh = C2.0 ma, v cc = v cc min 0.85 v cc v v oh2 i oh = C100 a, v cc = v cc min v cc C0.4 v lko low v cc lock-out voltage (note 4) 2.3 2.5 v
26 am29dl400b preliminary dc characteristics zero-power flash 20 15 10 5 0 0 500 1000 1500 2000 2500 3000 3500 4000 supply current in ma time in ns note: addresses are switching at 1 mhz 21606c-13 figure 9. i cc1 current vs. time (showing active and automatic sleep currents) 10 8 2 0 12345 frequency in mhz supply current in ma note: t = 25 c 21606c-14 figure 10. typical i cc1 vs. frequency 2.7 v 3.6 v 4 6
am29dl400b 27 preliminary test conditions table 7. test specifications key to switching waveforms 2.7 k w c l 6.2 k w 3.3 v device under te s t 21606c-15 figure 11. test setup note: diodes are in3064 or equivalent test condition -70, -80 all others unit output load 1 ttl gate output load capacitance, c l (including jig capacitance) 30 100 pf input rise and fall times 5 ns input pulse levels 0.0C3.0 v input timing measurement reference levels 1.5 v output timing measurement reference levels 1.5 v ks000010-pal waveform inputs outputs steady changing from h to l changing from l to h dont care, any change permitted changing, state unknown does not apply center line is high impedance state (high z) 3.0 v 0.0 v 1.5 v 1.5 v output measurement level input 21606c-16 figure 12. input waveforms and measurement levels
28 am29dl400b preliminary ac characteristics read-only operations notes: 1. not 100% tested. 2. see figure 11 and table 7 for test specifications. parameter description test setup speed options jedec std. -70 -80 -90 -120 unit t avav t rc read cycle time (note 1) min 70 80 80 120 ns t avqv t acc address to output delay ce#, oe# = v il max 70 80 80 120 ns t elqv t ce chip enable to output delay oe# = v il max 70 80 80 120 ns t glqv t oe output enable to output delay max 30 30 35 50 ns t ehqz t df chip enable to output high z (note 1) max 25 25 30 30 ns t ghqz t df output enable to output high z (note 1) max 25 25 30 30 ns t axqx t oh output hold time from addresses, ce# or oe#, whichever occurs first min 0 ns t oeh output enable hold time (note 1) read min 0 ns toggle and data# polling min 10 ns t oh t ce outputs we# addresses ce# oe# high z output valid high z addresses stable t rc t acc t oeh t rh t oe t rh 0 v ry/by# reset# t df 21606c-17 figure 13. read operation timings
am29dl400b 29 preliminary ac characteristics hardware reset (reset#) note: not 100% tested. parameter description all speed options unit jedec std t ready reset# pin low (during embedded algorithms) to read mode (see note) max 20 s t ready reset# pin low (not during embedded algorithms) to read mode (see note) max 500 ns t rp reset# pulse width min 500 ns t rh reset high time before read (see note) min 50 ns t rpd reset# low to standby mode min 20 s t rb ry/by# recovery time min 0 ns reset# ry/by# ry/by# t rp t ready reset timings not during embedded algorithms t ready ce#, oe# t rh ce#, oe# reset timings during embedded algorithms reset# t rp t rb 21606c-18 figure 14. reset timings
30 am29dl400b preliminary ac characteristics word/byte configuration (byte#) parameter -70 -80 -90 -120 jedec std. description unit t elfl/ t elfh ce# to byte# switching low or high max 5 ns t flqz byte# switching low to output high z max 25 25 30 30 ns t fhqv byte# switching high to output active min 70 80 90 120 ns dq15 output data output (dq0Cdq7) ce# oe# byte# t elfl dq0Cdq14 data output (dq0Cdq14) dq15/a-1 address input t flqz byte# switching from word to byte mode dq15 output data output (dq0Cdq7) byte# t elfh dq0Cdq14 data output (dq0Cdq14) dq15/a-1 address input t fhqv byte# switching from byte to word mode 21606c-19 figure 15. byte# timings for read operations note: refer to the erase/program operations table for t as and t ah specifications. 21606c-20 figure 16. byte# timings for write operations ce# we# byte# the falling edge of the last we# signal t hold (t ah ) t set (t as )
am29dl400b 31 preliminary ac characteristics erase and program operations notes: 1. not 100% tested. 2. see the erase and programming performance section for more information. parameter -70 -80 -90 -120 jedec std. description unit t avav t wc write cycle time (note 1) min 70 80 90 120 ns t avwl t as address setup time min 0 ns t aso address setup time to oe# low during toggle bit polling min 45 45 45 50 ns t wlax t ah address hold time min 45 45 45 50 ns t aht address hold time from ce# or oe# high during toggle bit polling min 0 ns t dvwh t ds data setup time min 35 35 45 50 ns t whdx t dh data hold time min 0 ns t oeph output enable high during toggle bit polling min 20 20 20 25 ns t ghwl t ghwl read recovery time before write (oe# high to we# low) min 0 ns t elwl t cs ce# setup time min 0 ns t wheh t ch ce# hold time min 0 ns t wlwh t wp write pulse width min 35 35 35 50 ns t whdl t wph write pulse width high min 30 ns t sr/w zero latency between read and write operations min 0 ns t whwh1 t whwh1 programming operation (note 2) byte typ 9 s word typ 11 t whwh2 t whwh2 sector erase operation (note 2) typ 0.7 sec t vcs v cc setup time (note 1) min 50 s t rb write recovery time from ry/by# min 0 ns t busy program/erase valid to ry/by# delay min 90 ns
32 am29dl400b preliminary ac characteristics oe# we# ce# v cc data addresses t ds t ah t dh t wp pd t whwh1 t wc t as t wph t vcs 555h pa pa read status data (last two cycles) a0h t ghwl t cs status d out program command sequence (last two cycles) ry/by# t rb t busy t ch pa notes: 1. pa = program address, pd = program data, d out is the true data at the program address. 2. illustration shows device in word mode. 21606c-21 figure 17. program operation timings oe# ce# addresses v cc we# data 2aah sa t ghwl t ah t wp t wc t as t wph 555h for chip erase 10 for chip erase 30h t ds t vcs t cs t dh 55h t ch in progress complete t whwh2 va va ry/by# t rb t busy notes: 1. sa = sector address (for sector erase), va = valid address for reading status data (see write operation status). 2 . illustration shows device in word mode. 21606c-22 figure 18. chip/sector erase operation timings
am29dl400b 33 preliminary ac characteristics oe# ce# we# addresses t oh data valid in valid in valid pa valid ra t wc t wph t ah t wp t ds t dh t rc t ce valid out t oe t acc t oeh t ghwl t df valid in ce# controlled write cycles we# controlled write cycle valid pa valid pa t cp t cph t wc t wc read cycle t sr/w 21606c-23 figure 19. back-to-back read/write cycle timings note: va = valid address. illustration shows first status cycle after command sequence, last status read cycle, and array data read cycle. 21606c-24 figure 20. data# polling timings (during embedded algorithms) we# ce# oe# high z t oe high z dq7 dq0Cdq6 ry/by# t busy complement true addresses va t oeh t ce t ch t oh t df va va status data complement status data true valid data valid data t acc t rc
34 am29dl400b preliminary ac characteristics oe# ce# we# addresses t oeh t dh t aht t aso t oeph t oe valid data (first read) (second read) (stops toggling) t ceph t aht t as dq6/dq2 valid data valid status valid status valid status ry/by# note: va = valid address; not required for dq6. illustration shows first two status cycle after command sequence, last status read cycle, and array data read cycle 21606c-25 figure 21. toggle bit timings (during embedded algorithms) note: dq2 toggles only when read at an address within an erase-suspended sector. the system may use oe# or ce# to toggle dq2 and dq6. 21606c-26 figure 22. dq2 vs. dq6 enter erase erase erase enter erase suspend program erase suspend read erase suspend read erase we# dq6 dq2 erase complete erase suspend suspend program resume embedded erasing
am29dl400b 35 preliminary ac characteristics temporary sector unprotect note: not 100% tested. parameter all speed options jedec std. description unit t vidr v id rise and fall time (see note) min 500 ns t rsp reset# setup time for temporary sector unprotect min 4 s t rrb reset# hold time from ry/by# high for temporary sector unprotect min 4 s reset# t vidr 12 v 0 v or 3 v ce# we# ry/by# t vidr t rsp program or erase command sequence 0 v or 3 v t rrb 21606c-27 figure 23. temporary sector unprotect timing diagram
36 am29dl400b preliminary ac characteristics sector protect: 100 s sector unprot ect: 10 ms 1 s reset# sa, a6, a1, a0 data ce# we# oe# 60h 60h 40h valid* valid* valid* status sector protect/unprotect verify v id v ih * for sector protect, a6 = 0, a1 = 1, a0 = 0. for sector unprotect, a6 = 1, a1 = 1, a0 = 0. 21606c-28 figure 24. sector protect/unprotect timing diagram
am29dl400b 37 preliminary ac characteristics alternate ce# controlled erase/program operations notes: 1. not 100% tested. 2. see the erase and programming performance section for more information. parameter -70 -80 -90 -120 jedec std. description unit t avav t wc write cycle time (note 1) min 70 80 90 120 ns t avwl t as address setup time min 0 ns t elax t ah address hold time min 45 45 45 50 ns t dveh t ds data setup time min 35 35 45 50 ns t ehdx t dh data hold time min 0 ns t ghel t ghel read recovery time before write (oe# high to we# low) min 0 ns t wlel t ws we# setup time min 0 ns t ehwh t wh we# hold time min 0 ns t eleh t cp ce# pulse width min 35 35 35 50 ns t ehel t cph ce# pulse width high min 30 ns t whwh1 t whwh1 programming operation (note 2) byte typ 9 s word typ 11 t whwh2 t whwh2 sector erase operation (note 2) typ 0.7 sec
38 am29dl400b preliminary ac characteristics t ghel t ws oe# ce# we# reset# t ds data t ah addresses t dh t cp dq7# d out t wc t as t cph pa data# polling a0 for program 55 for erase t rh t whwh1 or 2 ry/by# t wh pd for program 30 for sector erase 10 for chip erase 555 for program 2aa for erase pa for program sa for sector erase 555 for chip erase t busy notes: 1. figure indicates last two bus cycles of a program or erase operation. 2. pa = program address, sa = sector address, pd = program data, dq7# = complement of the data written to the device, d out = data written to the device. 3. waveforms are for the word mode. 21606c-29 figure 25. alternate ce# controlled erase/program operation timings
am29dl400b 39 preliminary erase and programming performance notes: 1. typical program and erase times assume the following conditions: 25 c, 3.0 v v cc , 1,000,000 cycles. additionally, programming typicals assume checkerboard pattern. 2. under worst case conditions of 90c, v cc = 2.7 v, 1,000,000 cycles. 3. the typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes program faster than the maximum program times listed. 4. in the pre-programming step of the embedded erase algorithm, all bytes are programmed to 00h before erasure. 5. system-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. see table 5 for further information on command definitions. 6. the device has a guaranteed minimum erase and program cycle endurance of 1,000,000 cycles. latchup characteristics includes all pins except v cc . test conditions: v cc = 3.0 v, one pin at a time. tsop and so pin capacitance notes: 1. sampled, not 100% tested. 2. test conditions t a = 25c, f = 1.0 mhz. data retention parameter typ (note 1) max (note 2) unit comments sector erase time 0.7 15 sec excludes 00h programming prior to erasure (note 4) chip erase time 10 sec byte program time 9 300 s excludes system level overhead (note 5) word program time 11 360 s chip program time (note 3) byte mode 4.5 13.5 sec word mode 2.9 8.7 min max input voltage with respect to v ss on all pins except i/o pins (including a9, oe#, and reset#) C1.0 v 12.5 v input voltage with respect to v ss on all i/o pins C1.0 v v cc + 1.0 v v cc current C100 ma +100 ma parameter symbol parameter description test setup typ max unit c in input capacitance v in = 0 6 7.5 pf c out output capacitance v out = 0 8.5 12 pf c in2 control pin capacitance v in = 0 7.5 9 pf parameter description test conditions min unit minimum pattern data retention time 150c 10 years 125c 20 years
40 am29dl400b preliminary physical dimensions* ts 04848-pin standard tsop (measured in millimeters) * for reference only. bsc is an ansi standard for basic space centering tsr04848-pin reverse tsop (measured in millimeters) * for reference only. bsc is an ansi standard for basic space centering. 48 25 1 24 18.30 18.50 19.80 20.20 11.90 12.10 0.05 0.15 0.50 bsc 0.95 1.05 16-038-ts48-2 ts 048 dt95 8-8-96 lv pin 1 i.d. 1.20 max 0.50 0.70 0.10 0.21 0.25mm (0.0098") bsc 0 5 0.08 0.20 48 25 1 24 18.30 18.50 19.80 20.20 11.90 12.10 seating plane 0.05 0.15 0.50 bsc 0.95 1.05 16-038-ts48 tsr048 dt95 8-8-96 lv pin 1 i.d. 1.20 max 0.50 0.70 0.10 0.21 0.25mm (0.0098") bsc 0 5 0.08 0.20
am29dl400b 41 preliminary physical dimensions (continued) so 04444-pin small outline (measured in millimeters) 44 23 1 22 13.10 13.50 15.70 16.30 1.27 nom. 28.00 28.40 2.17 2.45 0.35 0.50 0.10 0.35 2.80 max. seating plane 16-038-so44-2 so 044 df83 8-8-96 lv 0.10 0.21 0.60 1.00 0 8 end view side view top view
42 am29dl400b preliminary revision summary revision b expanded data sheet from advance information to pre- liminary version. revision c global changed -70r speed option to -70. figure 1, in-system sector protect/unprotect algorithm added pslscnt=1 to sector protect algorithm. reset command deleted last paragraph; applies only to hardware reset. dq6: toggle bit i first and second para., clarified that the toggle bit may be read at any address within the programming or erasing bank, not at any address. fourth para., clar- ified device to bank operating ranges deleted reference to regulated voltage range dc characteristics added note 4 reference to i cc6 and i cc7 . erase and program operations corrected note references for t whwh1 , t whwh2 , and t vcs temporary sector unprotect added note reference to t vidr . figure 24, sector protect/unprotect timing diagram updated figure to correct address waveformvalid ad- dress not required in first cycle. alternate ce# controlled erase/program operations corrected note references for t whwh1 , t whwh2 erase and programming performance in note 2, changed worst case endurance to 1 million cycles. trademarks copyright ? 1998 advanced micro devices, inc. all rights reserved. amd, the amd logo, and combinations thereof are registered trademarks of advanced micro devices, inc. expressflash is a trademark of advanced micro devices, inc. product names used in this publication are for identification purposes only and may be trademarks of their respective companies .

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